1. Field of the Invention
The present invention relates to a semiconductor device with a chip size package (hereinafter called “CSP: Chip Size (Scale) Package”) structure.
This application is a counterpart of Japanese patent application, Serial Number 169013/2003, filed Jun. 13, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
With a demand for downscaling of electronic equipment, miniaturization/densification of a semiconductor device has been made in recent years. Therefore, a semiconductor device having a CSP structure has been proposed wherein the shape of the semiconductor device is brought closer to a semiconductor element (chip) to reduce its size.
The semiconductor device having the CSP structure needs to increase the density of an array of external electrode terminals. Therefore, bump terminals (hereinafter called “bump electrodes”) are used which are electrically connected to their corresponding electrode pads as the external electrode terminals and extend vertically from a chip surface.
A general structure of this type of semiconductor device is shown in FIG. 4. In the same drawing, reference numeral 401 indicates a semiconductor substrate formed with an integrated circuit, reference numeral 402 indicates a electrode pad, reference numeral 403 indicates a passivation film, reference numeral 404 indicates an insulating film having an electrical insulating property similar to the passivation film 403, reference numeral 406 indicates a bump electrode, reference numeral 405 indicates a wiring between the electrode pad 402 and the bump electrode 406, reference numeral 407 indicates an encapsulating resin layer, and reference numeral 408 indicates an external terminal made up of solder for connection to the outside.
As a material for the insulating film 404, for example, polyimide relatively high in elasticity is used to relax stress applied to the external terminal 408 and the bump electrode 406 and prevent the occurrence of cracks in a semiconductor integrated circuit containing the passivation film 403 and the electrode pad 402. The thickness of the insulating film ranges from approximately 0.005 to 0.01 mm.
In order to reduce stress applied to the electrode pad 402, such layout design that the bump electrode 406 is formed at a position where it does not overlap with an opening (corresponding to a portion in which the insulating film 404 located directly above the electrode pad 402 does not exist) defined in the insulating film 404 when viewed from above is performed. The size of the opening defined in the insulating film 404 ranges from approximately 0.02 to 0.06 mm in diameter, and the size of the bump electrode 406 ranges from approximately 0.15 to 0.4 mm in diameter. This type of semiconductor device has been described in, for example, a patent document 1 (Japanese Laid Open Patent Application No. 2002-93945).